Survey of Optimization of FFT processor for OFDM Receivers

IJSRD Found one good Research work on Computer Engineering

IJSRD - International Journal for Scientific Research & Development| Vol. 1, Issue 2, 2013 | ISSN (online): 2321-0613

Nirav Chauhan1 Dr. Shruti Oza2 Dr. Kiran Parmar3 

1PG Student 2,3Associate Professer, Head

1,2Kalol Institute of Technology & Research Centre, Kalol, Ahmedabad, Gujarat, India 

3L.D. College of Engineering, Ahmedabad, Gujarat, India

Abstract— In the last few years wireless communications have experienced a fast growth due to the high mobility that they allow. However, wireless channels have some disadvantages like multipath fading that make them difficult to deal with. A modulation that efficiently deals with selective fading channels is OFDM. There are a large number of FFT algorithms and architectures in the signal processing literature. Therefore, the state of art algorithms and architectures should be analyzed and compared. Based on different algorithms and architectures, different power consumptions, area and speed of the processor will be achieved. So their ASIC suitability should be analyzed and the effort should be focused on the choosing algorithms and architectures and optimization. In this paper FFT Processor with Pipelined Architecture and CORDIC based ROM-free twiddle factor generator is proposed. The proposed algorithm and architecture should be validated by MATLAB simulation before implementation. After that, it is implemented on DSP Processor kit with Code Composer Studio. The synthesis results will be compared with other published FFT processor results.

Keywords: FFT, IFFT, DFT, Pipelining, Parallel Processing, Orthogonal Frequency Division Multiplexing (OFDM), Coordinate Rotation Digital Computer (CORDIC). 

I. INTRODUCTION

Orthogonal Frequency Division Multiplexing (OFDM) system is famous for its robustness against frequency selective fading channel. The Fast Fourier Transform (FFT) and Inverse FFT (IFFT) processor are used as the modulation/demodulation kernel in the OFDM systems. The sizes of FFT/IFFT Processors are varied in the different applications of OFDM systems. The terms Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) are used to denote efficient and fast algorithms to compute the Discrete Fourier Transform (DFT) and the Inverse Discrete Fourier Transform (IDFT) respectively. The FFT/IFFT is widely used in many digital signal processing applications and the efficient implementation of the FFT/IFFT is a topic of continuous research. 

During the last years, communication systems based on Orthogonal Frequency Division Multiplexing (OFDM) have been an important driver for the research in FFT/IFFT algorithms and their implementation. OFDM is a bandwidth efficient multiple access scheme for digital communications. Many of nowadays most important wireless communication systems use this OFDM technique: Broadcasting (DAB), Digital Video Broadcasting (DVB) (ETS, 2004), Wireless Local Area Network (WLAN) (IEE, 1999), Wireless Metropolitan Area Network (WMAN) (IEE, 2003) and Multi Band –OFDM Ultra Wide Band (MB–OFDM UWB) (ECM, 2005). Moreover, this technique is also employed in important wired applications such as Asymmetric Digital Subscriber Line (ADSL) or Power Line Communication (PLC). 

OFDM systems rely on the IFFT for an efficient implementation of the signal modulation on the transmitter side, whereas the FFT is used for efficient demodulation of the received signal. The FFT/IFFT becomes one of the most critical modules in OFDM transceivers. In fact, the most computationally intensive parts of an OFDM system are the IFFT in the transmitter and the Viterbi decoder in the receiver. The FFT is the second computationally intensive part in the receiver. Therefore, the implementation of the FFT and IFFT must be optimized to achieve the required throughput with the minimum penalty in area and power consumption. 

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